1. Field of The Invention
The present invention relates to a circuit for establishing accurate sample timing, and more specifically to such a circuit for use in a digital demodulator which forms part of an orthogonally multiplexed QAM (quadrature amplitude modulation) system. The accurate sample timing (or clock recovery) is assured by correcting the offsets of a preset sampling frequency and a preset sampling phase through the use of control loops provided in the demodulator.
2. Description of the Prior Art
It is known in the art that an orthogonally multiplexed parallel data transmission system allows spectrum overlappings within a predetermined bandwidth, and hence attains a very high data transmission efficiency close to the efficiency of the ideal Nyquist transmission. Such a transmission system therefore has found demand in arrangements wherein very high efficiencies of digital transmission are important.
In such a transmission system, parallel data are transmitted through a plurality of channels by modulating two carrier components 90.degree. apart in phase of each channel, while maintaining the orthogonality of adjacent channels.
In order to recover transmitted baseband signals in the digital demodulator, it is vital to accurately sample received analog signals. The accurate sample timing is assured by eliminating or compensating for sampling frequency and phase offsets within the demodulator. The frequency offset is a phase deviation of a received complex signal, which rotates in phase as a function of time, while the phase offset is a static or time-invariant phase deviation of a received complex signal.
In order to establish the correct sample timing, it is a common practice to utilize phase offset information which is obtained from a tapped delay line type automatic equalizer. This phase offset information is used to control a voltage-controlled oscillator which is adapted to control a sampling frequency (viz., sample timing) of a sampler. More specifically, in the case a sampling phase offset exists, the center tap of the automatic equalizer varies in position. The quantity of sampling phase deviation is detected by means of tap coefficient variations and is fed back, through a control loop, to the voltage-controlled oscillator so as to control same.
The above-mentioned automatic equalizer has been intended to correct static interchannel and intersymbol interferences and to prevent the degradation of a signal-to-noise (S/N) ratio caused by white noise. This is the reason that the control loop gain is set to a small value. Consequently, in the case where a large frequency offset takes place after the system is initially operated (for example), the automatic equalizer is unable to correct the resultant rapid phase shifts because the control loop gain is set to a small value, and hence fails to establish a correct sample timing in such an initial duration (for example).
For further details relating to the principle of an orthogonally multiplexed QAM system and the automatic equalizer for use therein, reference should be had to the article entitled "An Analysis of Automatic Equalizers for Orthogonally Multiplexed QAM Systems", IEEE Transactions on Communications, Vol. Com-28, No. 1, January 1980, PP. 73-83. Further, a Modem (modulator-demodulator) for use in an orthogonally multiplexed QAM system has been disclosed in Japanese patent application No. 55-28740 (laid open under the publication No. 56-125131).